Seminar

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CMOS fundamentals for ASIC design

• Date : Nov 9, 2000
• PostScript File (2.5MBytes)
• LaTeX source File (18kBytes) (figure files are not included.)
  1. CMOS Device physics
     • Band diagram
     • Threshold voltage
     • Body effect
  2. Input buffer
     • Schmitt trigger
  3. Output buffer
     • Open drain
     • Tri-state buffer
     • Totem-pole output buffer
     • Supply bounce (Ground bounce)
     • Latup
     • ESD
  4. CMOS consideration for ASIC design
     • Logic Family : CMOS, TTL

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VHDL

• Date : Aug 24, 2000
• Abstract : Basic concept about VHDL & General syntax of VHDL and its overview.
• PostScript File (631KBytes)
  1. Domains and Levels of modeling
  2. VHDL strucure
  3. Extended Backus-Naur Form
  4. Modeling Method
     • Behavior Modeling
     • Data flow Modeling
     • Structural Modeling
  5. VHDL for Synthesis

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Logic synthesis using SYNOPSYS Design Compiler

• Date : Oct 4, 2000
• Abstract : Synthesis concept, basic constraints for synthesis.
• Postscript file (2.1MByte)
• LaTeX file (4.1KByte) (figure files are not included.)
  1. Brief introduction to Synthesis
  2. Specifying the Technology Requirement
  3. Defining the Design Environment
  4. Setting Design Constraints
  5. Partitioning & Coding Styles for Sythesis
  6. Optimizing your design
  7. Selecting a compile strategy.

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